1. Field of the Invention
This invention relates generally to a process for fabricating bipolar transistors and, more particularly, to a process for fabricating heterojunction bipolar transistors having relatively thin intrinsic collector regions and relatively thick extrinsic collector regions.
2. Discussion of the Related Art
Heterojunction bipolar transistors (HBTs) which incorporate a base and a collector of one semiconductor material, typically gallium arsenide (GaAs), and an emitter of a second semiconductor material, typically aluminum-gallium-arsenide (AlGaAs), are known in the art. HBT devices are popular because of a number of well known advantages over their homojunction bipolar transistor counterparts. These advantages include high speed, a high third order intermodulation product (IP3), a low noise/power ratio, and high current drive capabilities. These advantages provide a wide range of diverse functions of HBT devices for many commercial and industrial applications such as in communications and electronic warfare.
The performance of HBT devices critically depends on the thicknesses of the emitter, base, collector and sub-collector layers which form the transistor. In fabricating HBT devices, these thicknesses are generally accurately controlled by the semiconductor growth process of molecular beam epitaxy (MBE), well known to those skilled in the art. For high speed performances, the HBT devices are grown with very thin base and collector layers for providing short electron transit times through these layers. The area of the HBT device in which the base and collector must be very thin to provide desirable transit times is generally referred to as the intrinsic region, and is located directly below an emitter mesa making up the emitter. The area surrounding the intrinsic region, generally referred to as the extrinsic region, has no effect on electron transit time and therefore can be of any thickness. Since HBT devices are usually fabricated with one single MBE growth, the thickness of the extrinsic and intrinsic regions are generally the same.
An additional limiting factor for high speed performance of the HBT devices is the capacitance which is created at the base-collector interface due to the voltage drop across this junction. A typical base-collector voltage bias of an HBT device causes a separation of negative and positive charges to develop across the base-collector interface with the negative charges stored in the base layer and the positive charge stored in the sub-collector layers. Thus, the capacitance at this base-collector junction is, to a first approximation, equal to a parallel plate capacitor with the cathode and anode as the base and sub-collector, respectively. For high speed operations, this capacitance must be reasonably small. Therefore, the collector layer has to be correspondingly thick since the thickness of the collector layer is inversely proportional to the capacitance. The area of the HBT device where the collector layer must be thick to reduce capacitance is the extrinsic region.
As becomes clear from this discussion, the HBT device needs to satisfy both of the requirements of short electron transit times and low capacitance in order to realize a high speed device. Attempts have been made in the prior art to provide an HBT device having a thin collector layer for short electron transit times, but also having a reduced base-collector capacitance. One of those attempts deals with the implantation of impurities into the collector layer in order to damage the lattice structure outside of the active area of the transistor, and thus, reduce the base-collector capacitance. This process has the effect, however, of reducing the doping concentrations in the collector. See Ota, Y. et al., "Properties of MBE-Grown and 0+ Implanted GaAs And Their Application to the Formation of a Buried Collector of an AlGaAs/GaAs HBT", J. Appl. Phys. 64(2), 15 Jul. 1988. Additionally, attempts have been made at fabricating collector-up HBTs in which the base-collector junction area has a smaller area than the emitter-base junction. This configuration thus eliminates the extrinsic base-collector junction area. See Asbeck, P. et al., IEEE Electron Devices Letter Edl-5, 310 (1984).
Each of the attempts in the prior art to reduce base-collector capacitance while maintaining a thin collector layer, although somewhat successful, have led to one or more of the following drawbacks: a decrease in the semiconductor crystal quality which leads to a degradation in current gain, a reduction in reliability due to the diffusion of implanted impurities during high temperature and/or high voltage operation, and an increase in processing complexity. It is therefore an object of the present invention to provide a novel HBT structure which has both the base-collector capacitance and collector layer thickness minimized while avoiding the drawbacks mentioned above.